1. Field of the Invention
The present invention relates to an address setting and filtering system for terminal accommodating circuits to be connected between data terminals for sending and receiving packet information on a high speed packet transmission bus.
2. Description of the Prior Art
In recent years, packet switching systems have come to be extensively used, and the development of communication networks in local area networks has made significant progress. Governmental bodies, communication companies and manufacturers in many countries of the world have announced plans for and started the implementation of the systematization of integrated service networks.
Where terminal units are to be accommodated into a high speed digital transmission bus (hereinafter referred to as simply "high speed bus"), since the coded information handled by the terminals themselves is low in transmission speed, the point of connection to the high speed bus should be equipped with a high speed interface, about 10 times as fast or even faster.
Thus, according to a known technique, each terminal unit is connected to a terminal accommodating circuit of the packet switching system via a low speed terminal transmission path, and this terminal accommodating circuit has an interface with the high speed transmission bus of the packet switching system to send and receive packets.
Therefore, each terminal accommodating circuit requires the registration of its specific terminal addresses, so that packet frames which should arrive at the terminal units accommodated in the circuit can be taken out of the high speed transmission bus.
Meanwhile, according to the transmission procedure of the packet switching system conforming to the CCITT Recommendation and the IEEE Standards, it is necessary to insert the address of the originating source into the source packet frame and to check the identity of the destination address in the received packet frame. The terminal unit also requires the registration of the terminal address assigned to it in a specific address memory. Accordingly, in an address setting system of this kind in the prior art, a terminal address is set and registered for each individual terminal unit, and the same terminal address is registered in the corresponding terminal accommodating circuit.
FIG. 1 is a functional block diagram illustrating one example of the prior art. In FIG. 1, terminal units 10 are accommodated into terminal accommodating circuits 90, which are connected to a high speed transmission bus 40.
Each of the plural terminal units 10 has a specific address memory 11, a packet forming section 12, a packet distinguishing section 13 and a data processing unit 14. Each of the plural terminal accommodating circuits 90 has a packet identifying section 91, a high speed code sending section 22, a terminal address memory 23, a high speed code receiving section 24, a packet detecting section 25 and an address filter 96. Meanwhile, the central control unit 30 of the packet switching system takes out a terminal address from a terminal address book 39, in which the map of terminal addresses is stored, and registers it in each of the terminal accommodating circuits 90. A packet sent and received in this packet switching system, as illustrated in FIG. 2, comprises, for instance, a packet start flag FLS, a destination address DA, a source address SA, data length information LEN, packet data DATA, error detection information FCS and a packet end flag FLE.
The specific address memory 11 of the terminal unit 10 stores the terminal address assigned to this terminal in the communication network. The packet forming section 12, when forming a source packet frame (FIG. 2), inserts the address taken out of the memory 11 into the packet frame the source address SA. Meanwhile, the packet distinguishing section 13, upon receiving the packet frame from the circuit 90 via a low speed transmission bus 15, extracts the destination address DA and, after checking the identity between this destination address DA and the terminal address taken out of the memory 11, takes the packet information into the data processing unit 14 within the terminal unit 10.
On the other hand, the packet identifying section 91 of the circuit 90 identifies the packet frame received from the terminal unit 10, and transfers it to the high speed code sensing section 22 to have it sent to the high speed bus 40. In the terminal address memory 23 the terminal address is already registered and recorded into the address book 39 by the central control unit 30, corresponding to the terminal unit to be accommodated. The high speed code receiving section 24 receives a high speed code from the high speed bus 40, and the packet detecting section 25 detects, the packet frame and supplies it to the address filter 96. The filter 96 takes out the destination address DA from the received packet frame and the terminal address from the terminal address memory 23, compares them and, if they are found identical, transfers this packet to the packet distinguishing section 13 of the terminal unit 10.
Therefore, a specific terminal address assigned to a given terminal unit 10 is set into both the specific address memory 11 of the unit 10 and the terminal address book 39, and should also be registered by the central control unit 30 into the memory 23 of the terminal accommodating circuit 90 which connects this terminal unit 10.
This address setting system in the prior art, so structured as to register the same terminal address in a terminal unit and a position in the terminal address book corresponding to the terminal accommodating circuit, involves the trouble of setting the same registration in two positions, and also entails the risk of wrong setting.